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BARC 2020: Computer Organisation Nuclear Quiz 1 (App update required to attempt this test)

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Question 1

Let the address stored in the program counter be designated by the symbol X1.The instruction stored in X1 has an address part (operand reference) X2. The operand needed to execute the instruction is stored in the memory word with address X3.An index register contains the value X4.What is the relationship between these various quantities if the addressing mode of the the instruction is Indexed Addressing Mode?

Question 2

Consider the following instruction sequence:
I1: R1 = 100
I2: R1 = R2 + R4
I3: R2 = R4 – 25
I4: R4 = R1 + R3
I5: R1 = R1 + 30
The number of RAW, WAR, WAW dependencies are?

Question 3

Assume an instruction set that uses a fixed 16-bit instruction length. Operand specifiers are 6 bits in length. There are K two-operand instructions and L zero-operand instructions. What is the maximum number of one-operand instructions that can be supported?

Question 4

Consider the following statement regarding CISC computer:
S1: It supports more addressing modes.
S2: It contains large instruction set.
S3: It is more suitable for general purpose system.
Which of the following is false?

Question 5

The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is _________ percent.

Question 6

Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is _____.

Question 7

If the last operation performed on a computer with an 8-bit word was an addition in which the two operands were 00000010 and 00000011,what would be the value of the following flags (Carry, Zero, Overflow, Sign, Even-Parity, Half-Carry)?

Question 8

Consider the Following IEEE 32 bit representation:

0 01111110 10100000000000000000000

Its decimal equivalent is ___________ (Upto 4 decimal places)

Question 9

The memory locations 200, 201 and 210 have data values 6, 2 and 3 respectively before the following program is executed.

Question 10

Using Booth's Algorithm for multiplication, the multiplier -57 will be recoded as

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GATE & PSU CS Computer Organization and Architecture

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