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BARC 2018 EE:Digital Electronics Nuclear Quiz 3
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Question 1
For the output F to be 1 in the logic circuit shown, the input combination should be
Question 2
In the figure shown, the output Y is required to be Y = AB + . The gates G1 and G2 must be, respectively,
Question 3
The increasing order of speed of data access for the following devices is
(i) Cache Memory (ii) CDROM
(iii) Dynamic RAM (iv) Processor Registers
(v) Magnetic Tape
(i) Cache Memory (ii) CDROM
(iii) Dynamic RAM (iv) Processor Registers
(v) Magnetic Tape
Question 4
For the logic circuit shown in the below figure, the simplified Boolean expression for the output Y is
Question 5
A 3 bit module-8 ripple counter uses JK flip-flop. If the propagation delay of each FF is 40ns, the maximum clock frequency that can be used is equal to
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Jul 20ESE & GATE EE