Collection of instructions.
Each instruction has a unique bit pattern, but for human beings, a corresponding symbolic representation has been defined.
The instruction cycle consists of the following phases
- Fetching an instruction from memory.
- Decoding the instruction.
- Reading the effective address from memory in case of the instruction having an indirect address.
- Execution of the instruction.
- Writing the results back to the memory.
An instruction consists of bits and these bits are grouped up to make fields.
Some fields in instruction format are as follows
- Opcode which tells about the operation to be performed.
- Address field designating a memory address or a processor register.
- Mode field specifying the way the operand or effective address is determined.
Different types of Instruction formats
Some common types are: Three address instruction format, Two address instruction format, One address instruction format, and Zero address instruction format.
- Three Address Instruction Format: This system contains three address fields (address of operand1, address of operand2 and address where the result needs to be put). The address of next instruction is held in a CPU register called Program Counter (PC).
Here, the number of bytes required to encode an instruction is 10 bytes.
Each address requires 24 bit = 3 bytes.
Since there are three addresses and one opcode field.
Therefore 3 × 3 + 1 = 10 bytes.
The number of memory access required is 7 words.
4 words for instruction fetch, 2 words for operand fetch and 1 word for the result to be placed back in memory.
- Two Address Instruction Format: In this format, two addresses and an operation field is there. The result is stored in either of the operand address i.e., either an address of the first operand or in the address of the second operand. CPU register called Program Counter (PC) contains the address of next instruction.
- One Address Instruction Format: One address field and an operation field. This address is of the first operand. The second operand and the result are stored in a CPU register called Accumulator Register (AR). Since a machine has only one accumulator, it needs not to be explicitly mentioned in the instruction. A CPU register (i.e., Program Counter (PC) holds the address of next instruction. In this scenario, two extra instructions are required to load and store the accumulator contents.
The number of bits required to encode an instruction is 4 bytes. i.e., each address requires 24 bits = 3 bytes. Since, there are one address and one operation code field, 1* 3 + 1= 4 bytes.
The number of memory access required is 3 words i.e., 2 words for instruction fetch +1 word for code for operand fetch.
- Zero Address Instruction Format: Stack is included in the CPU for performing arithmetic and logic instructions with no addresses. The operands are pushed onto the stack from memory and ALU operations are implicitly performed on the top elements of the stack. The address of the next instruction is held in a CPU register called program counter.
Top of stack ← Top of stack + second top of the stack.
The different ways in which the location of an operand is specified in instruction are referred to as addressing modes.
Types of Addressing Modes
Memory Based Addressing Modes:
- Implied Addressing Mode: In this mode, the operands are specified implicitly in the definition of instruction.
- Immediate Addressing Mode: In this mode, the operand is specified in the instruction itself or we can say that an immediate mode instruction has an operand rather than an address.
- Direct Register Addressing Mode: In this mode, one of the operands is in registers and other is taken from memory.
- Direct Addressing Mode: It this mode, the address of the memory location that holds the operand is included in the instruction. The effective address is the address part of the instruction.
- Indirect Addressing Mode: In this mode, the address field of the instruction gives the address where the effective address is stored in memory.
- Relative Addressing Mode: In this mode, the content of the program counter is added to the address part of the instruction to calculate the effective address.
- Indexed Addressing Mode: In this mode, the effective address will be calculated as the addition of the content of the index register and the address part of the instruction.
Transfer Of Control Addressing Modes:
- PC Relative Addressing Mode: This addressing mode is used to access the instruction within the segment, therefore only one offset address is required.
- Base register Addressing Mode: This addressing mode is used to access the instructions between two segments. Therefore, base address, as well as offset, is required.
Types of Instructions
- Data Transfer Instructions: Data transfer instructions cause the transfer of data from one location to another without changing the information content. The common transfers may be between memory and processor registers, between processor registers and input/output.
Typical Data Transfer Instructions
- Data Manipulation Instructions: Data manipulation instructions perform operations on data and provide the computational capabilities for the computer. There are three types of data manipulation instructions: Arithmetic instructions, Logical and bit manipulation instructions, and Shift instructions.
Typical Arithmetic Instructions
Typical Logical and Bit Manipulation Instructions
Typical Shift Instructions
Program Control Instructions
Program control instructions specify conditions for altering the content of the program counter, while data transfer and manipulation instructions specify conditions for data processing operations. The change in value of a program counter as a result of the execution of a program control instruction causes a break in the sequence of instruction execution.
Typical Program Control Instructions
The program interrupts are used to handle a variety of problems that arise out of normal program sequence.
- Program interrupts are used to transfer the program control from a currently running program to another service program as a result of an external or internal generated request. Control returns to the original program after the service program is executed.
Types of Interrupts
Interrupts can be classified into two categories:
On the basis of Masking
- Maskable Interrupts: It may be a hardware or a software interrupt which can be masked for the future.
- Non-Maskable Interrupts: A non-maskable interrupt (NMI) is a hardware interrupt that standard interrupt-masking techniques in the system cannot ignore. It typically occurs to signal attention for non-recoverable hardware errors.
On the basis of devices
- External interrupt: External interrupts come from Input-Output (I/O) devices or from a timing device.
- Internal interrupt: Internal interrupts arise from illegal or erroneous use of an instruction or data. External and internal interrupts from signals that occur in the hardware of the CPU.
- Software interrupt: A Software interrupt is initiated by executing an instruction.
Complex Instruction Set Computer (CISC)
- Computer architecture is described as the design of the instruction set for the processor.
- The computer with a large number of instructions is classified as a complex instruction set computer. The CISC processors typically have the 100 to 250 instructions.
- The instructions in a typical CISC processor provide direct manipulation of operands residing in memory.
- As more instructions and addressing, modes are incorporated into a computer, the more hardware logic is needed to implement and support them and this may cause the computations to slow down.
Reduced Instruction Set Computer (RISC)
- RISC architecture is used to reduce the execution time by simplifying the instruction set of the computer.
- In the RISC processors, there are relatively few instructions and few addressing modes. In RISC processors, all operations are done within the registers of the CPU.
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