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Instruction Pipelining GATE 2024 Fundamental Quiz
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Question 1
For a given system pipeline, speedup factor is 8.4 and it operates at 100MHZ with 60% efficiency. The number of stages in pipelines are _________.
Question 2
Consider an instruction pipeline which has 4-stages with the respective stages delays as 10ns, 30ns, 20ns, 5ns. Interface registers used between the stages have a delay of 5ns. What is the approx speedup?
Question 3
Program runs for 100 seconds on a uniprocessor. 10% of the program can be parallelized on a Multiprocessor (F = 0.1). Assume a Multiprocessor with 10 processors (n = 10). Compute the speedup.
Question 4
Which of the following dependency problem can be eliminated by using Register Renaming technique?
Question 5
Consider instruction pipeline with a speedup 22 while operating with 73% efficiency.
What can be the number of stages in the pipeline?[in the nearest integer]
Question 6
Read the below statements and choose the correct option regarding the pipeline?
S1: Instruction dependency refers to the case where by fetching an instruction depends on the results of previously executed instruction.
S2: Data dependency in a pipeline occurs when a source operand of an instruction depends on the results of previously executed instruction.
S3: Instruction dependency can lead to fetching of the wrong instruction.
S4: Data dependency can lead to fetching of the wrong operand.
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Jan 19GATE & PSU CS