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IIIT Hyderabad Practice Quiz : Digital Logic-1
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Which one of the following statement is true when the function is having cyclic prime implicant K-map?
The output of a 3-input logic circuit f(x, y, z) is 1 if ax + by + cz < d and 0, otherwise (a, b, c, d are constant). For what values of a, b, c, d does this represent an implementation of the AND gate.
The simplification of the Boolean expression (P’QR’)’ + (PQ’R)’ is….
For the circuit shown below find out the canonical form of the output f(A,B,C)
What will be the state of the output after the 3rd clock to the given circuit.
Assume initially QA = 0, QB = 0
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Mar 14GATE & PSU CS
Priya UpadhyayMember since Sep 2020Priya Upadhyay