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IIIT Hyderabad Practice Quiz : Computer organization-3

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Question 1

Consider 4-segement instruction pipeline where different instruction are spending different amount of time at different stages shown below:

How many cycles are required to complete the above instruction in case of a pipelined processor and also for non-pipelined processor?

Question 2

Assume a computer has on-chip and off-chip caches, main memory and virtual memory. Assume the following hit rates and access times: on-chip cache 95%, 1 ns, off-chip cache 99%, 10 ns, main memory: X%, 50 ns, virtual memory: 100%, 2,500,000 ns. Notice that the on-chip access time is 1 ns. We do now want our effective access time to increase much beyond 1 ns. Assume that an acceptance effective access time is 1.6 ns. What should X be (the hit rate of memory) to ensure that EAT is no worse than 1.6 ns?

Question 3

What is the sum and difference of 0x01 and 0xFF in Two’s complement form ?___

Question 4

Which of the following affects the processing power?

Question 5

Assume that the control memory is 24 bits wide. The control portion of the microinstruction format is divided into two fields. A micro-operation field of 13 bits specifies the micro-operations to be performed and An address selection field specifies a condition, based on the flags that will cause a microinstruction branch. There are eight flags. The control unit that adopts the single address field branch control logic.
a. How many bits are in the address selection field?
b. How many bits are in the address field?
c. What is the size of the control memory?
What is the answer to the above questions?
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Mar 20GATE & PSU CS

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Priya UpadhyayPriya UpadhyayMember since Sep 2020
Priya Upadhyay
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