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GATE EC 2022: EDC Quiz 6 (App update required to attempt this test)

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Question 1

The parameter for an ideal npoly-Si gated MOSFET are as follows : L=0.5 μm, w=2.5 μm, tox = 10 nm, and VT= 0.5V 

The Gate voltage , VGS, that must be applied to obtain the ID-VD  curve shown is ___________(V).

Question 2

In an n-channel MOSFET , drain is shorted to the gate so that VGS = VDS.  And V=1V. If the drain current ID is 1 mA for VGS =2V then for VGS =3V, ID  (in mA) is

Question 3

Consider an n+ polysilicon-silicon dioxide n-type silicon MOS capacitor. Let Nd = 1015 cm-3, tox =, and . What will be the flat-band voltage? If

Question 4

The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be 1 mA at a drain-source voltage of 5 V. When the drain-source voltage was increased to 6V while keeping gate-source voltage same, the drain current increased to 1.02 mA. Assume that drain to source saturation voltage is much smaller than the applied drain-source voltage. The channel length modulation parameter (in V–1) is ____.

Question 5

The drain of an n-channel MOSFET is shorted to the gate so that VGS = VDS . The threshold voltage (VT) of MOSFET is 1V. If the drain current (ID) is 1 mA for VGS = 2V, then for VGS = 3V, ID is

Question 6

In the three dimensional view of a silicon n-channel MOS transistor shown below. δ = 20 mn. The transistor is of width 1 µm. The depletion width formed at every p-n junction is 10 mn. The relative permittivities of Si and SiO2, respectively, are 11.7 and 3.9. and ε0 = 8.9 x 10–12 F/m.

The gate-source overlap capacitance is approximately
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Jun 13ESE & GATE EC

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V V Satya Narayana MadasuV V Satya Narayana MadasuMember since Sep 2020
Gate Qualified in 2018,2019,2020,2021| ISRO Exam qualified| AIR -672|Completed M.Tech in VLSI Design
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