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# GATE EC 2022: Digital Circuits Quiz 6

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Question 1

Consider the circuit given below.

The duty cycle of is

The duty cycle of is

Question 2

Consider the circuit given below

Assuming the initial value of counter output (

Assuming the initial value of counter output (

**Q**) as zero, the counter output for 8 clock pulses in decimal form is_{1}, Q_{o}Question 3

The present output Q

_{n}of an edge triggered JK flip-flop is logic 0. If J=1, then Q_{n +1}Question 4

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input „In‟ and an output ‘Out’. The initial state of the FSM is S0.

If the input sequence is 10101101001101, starting with the left-most bit, then the number times ‘Out’ will be 1 is __________.

If the input sequence is 10101101001101, starting with the left-most bit, then the number times ‘Out’ will be 1 is __________.

Question 5

What will be the frequency of the output if the input frequency is 200kHz?

Question 6

For the flip flop configuration shown below find the operation carried out by this configuration.

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Sep 17ESE & GATE EC

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