Sequential Circuits-2 Study Notes for GATE CS Exam

Flip Flop Conversions

The flip flop conversions are classified into various types, which are as follows:

• SR-FF to D-FF Conversion
• D-FF to SR-FF Conversion
• SR-FF to JK-FF Conversion
• JK-FF to SR-FF Conversion
• JK-FF to D-FF Conversion
• D-FF to JK-FF Conversion
• JK-FF to T-FF Conversion

Procedure for Converting Flip Flop:

1. Conversion Table: Design and construct the characteristic table of required flip flop (unknown, into which we want to convert), and fill available (known, flipflop which is to be converted) flip flop excitation table.
2. Solve the K map for the given (known) flip flop as input and the desired flip flop.
3. Make use of the given(known) flip flop to implement the required flip flop.

Example: Conversion from JK to D flip flop is shown as:

Characteristic Table

Characteristic Table

Registers

A group of flip flops is used to store a word (group of bits). n flip flops are cascaded to store n bits in the register. The register in which binary information can be moved from one stage to another; this type of register is called shift registers. Shift registers are classified according to data movement in a register, and shift registers are as follows: 

1. Parallel Input Serial Output (PISO)
2. Parallel Input Parallel Output (PIPO)
3. Serial Input Serial Output (SISO)
4. Serial Input Parallel Output (SIPO)

Serial Input Serial Output (SISO)

• An edge trigger circuit is used to make the circuit synchronous in the register.
• If no clock is applied, then get the same data that is stored.
• In N bits, the SISO register provides N bits data, Serially out require (N-1) clock pulse, and Serially in requiring N clock pulse.

Serial Input Parallel Output (SIPO)

• To provide N-bit data: Serial in requiring N clock pulse, and Serial out no clock pulse require
• SIPO can convert temporal code or serial data to parallel or serial code.
• SIPO can provide n × tCIK delay to the input.

Parallel Input Serial Output (PISO)

• If control = 1, then it acts as serial output;
• If control = 0, then it acts as parallel input;
• One clock pulse is required to provide parallel input.
• To provide N bits serial output, it requires (N-1) clock pulse.
• PISO can convert special code to temporal code.

Parallel Input Parallel Output (PIPO)

• In the PIPO register for parallel input number of pulse required is one clock pulse.
• In the PIPO register for parallel output number of pulse required is 0 clock pulse.
• PIPO register cannot be used as a shift register.
• It is used for temporal storage of data in microcontroller, DSP, CPU etc.

Summary of Registers

Counter

• It is a sequential logic circuit capable of counting the total number of clock pulses arriving at its clock input.
• The sequence of count may be ascending, descending or non-sequence.
• For a counter circuit having n flip flops, Maximum possible states (N) = 2n
• If N = 2n, the counter acts as a binary counter.
• If N < 2n, the counter non-binary counter.
• It counter is capable of counting from 0 to 2n-1.
• MOD number is the number of states present in a counter is known as modulus count or MOD number.
• For n-flip flops, the counter will have 2n different states, and then this counter is said MOD- 2n counter.

MOD-M Counter:

• MOD number shows the frequency division obtained from the last flip flops.

• Cascaded two counters:

• MOD-MN counter:
  • Overall states of combined counter = MN
  • Input frequency = f
  • Output frequency f = f/(MN)

Classification of Counters:

Counters are classified into two categories according to the applying clock pulse.

1. Synchronous counter
2. Asynchronous counter (ripple counter)

Toggle Mode Circuit: Toggle mode circuits are frequency dividers circuits.

Other Toggle Mode Circuit:

Asynchronous Counter (Ripple counter):

• The different clock pulse is applied to different flip flops.
• All flip flops are operating in toggle mode.
• In asynchronous counter flip flop applied with external clock acts as LSB bit.

3-bit Ripple Up Counter

• The input clock is applied at LSB bit.
• It n-bit ripple counter maximum possible states are 2n.
• Bit ripple up counter counts from 0 to 2n – 1.
• If all states are used then with input frequency f, then output frequency will be f/2n
• Calculation of Time Period of Flip Flop: In the n-bit ripple counter, if the propagation delay of each flip flop is tpd(FF), then the time period of the clock is:

TCLK ≥ ntpd(FF)

• Maximum Clock Frequency:

• Due to propagation delays of flip flops decoding errors are present.
• Clear and preset are known as asynchronous input to flip flop.
• In any ripple counter, the following conditions will fulfil
  • Negative edge trigger and Q as clock ⇒ up counter
  • Positive edge trigger and Q as clock ⇒ up counter

3-bit Ripple Down Counter

• Positive edge trigger and Q as clock ⇒ down counter
• Negative edge trigger and Q as clock ⇒ down counter

Non-binary Ripple Counter: Decode counter or BCD counter is an example of a non-binary counter. It requires 4 flip flops.

• Used state = 10 and unused states = 6 → (2⁴ -10)
• Output frequency of BCD counter = f/10
• For making non-binary counter clear (CLR) signal is used.
• c1r is active high, and (CLR)’ is active low.

Synchronous Counters:

There are no connections of the first flip flop output to the clock input of the next flip flop in this type of counter.

Ring Counter: It is a circular shift register with only a flip flop being set at any particular time; all others are cleared. It is a shift register with feedback.

• • In-ring counter, if feedback is used Number of states is reduced.
  • With n flip flops, maximum states = n.
  • Number of unused states in-ring counter = 2n – n
  • Maximum Clock Frequency: If the input frequency is f, then at the output of every flip flop, we get f/N frequency. In-ring counter, if the propagation delay of each flip flop is tpd(FF), then.

  TCLK ≥ tpd(FF);

Jhonson Ring Counter: It is also called a Twisted ring counter, Switch tail counter, Creeping counter, or Mobies counter.

• In n – bit Jhonson counter maximum used states = 2n, unused states = 2n – 2n.
• If the input clock frequency is f, then the output frequency of each flip flop is f /2n, and the duty cycle is 50%.
• The disadvantage of the Jhonson Ring Counter: Lockout may occur. To decode each state, one, two-input AND or NOR gate is used.

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