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GATE CS 2022: Digital Logic-4

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Question 1

When one of the inputs of a two-input XOR gate is at Logic Low, the output will be _____ as the other input.

Question 2

The minimum number of 2-input NAND gates Y required to implement the function F = (x' + y') (z + w) is

Question 3

Consider the below circuit:

The propagation delay of each multiplexer is 50 ns. The frequency of the output signal V is

Question 4

Consider the following sequential circuit consisting of 2 J-K flip flops and D flip flop :

The Mod value for this counter is_____________.

Question 5

The number of unused states in a 4 bit Johnson counter is ______.

Question 6

Consider the following circuit

The minimum number of NAND gate (having 2 fan-in) require to implement the same circuit is___. Assume complements of each variable are already available.

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Jul 19GATE & PSU CS

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Priya UpadhyayPriya UpadhyayMember since Sep 2020
Priya Upadhyay
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