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GATE CS 2022: Digital Logic-2 (App update required to attempt this test)

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Question 1

Given logical function f= AB+ (AC)’ + AB’C(AB+ C) is same as which of the following

Question 2

Minimize the following canonical expression using the Boolean law ABC'D' + ABC'D + AB'C'D + ABCD + AB'CD + ABCD' + AB'CD'

Question 3

If X = 111101 and Y = 000100 be two 8-bit 2’s complement numbers. Their product in 2’s complement is:

Question 4

Which of the following statements is/are correct

1) A flip-flop is used to store 1 bit of information only.

2) Race around condition occur in JK flip flop when both of its input are 1.

3) Master Slave configuration is used in flip flop to store two bit of information.

4) A transparent latch consist of D-type flip flop.

Question 5

If a Full Adder is taking 20ns to produce carry and 40ns to produce sum. The maximum frequency of 4-bit parallel addition in MHz is________.

Question 6

Number of minimal SOP expression is ______, which is represented by following k-map

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May 30GATE & PSU CS

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Priya UpadhyayPriya UpadhyayMember since Sep 2020
Priya Upadhyay
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