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GATE CS 2022 : Computer Organization Quiz-9

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Question 1

Which among the following is incorrect about DMA?

Question 2

Regarding the different modes of data transfer, the throughput of CPU are measured: T1 for burst mode, T2 for cycle stealing mode, T3 for transparent DMA. Which of the following is best option?

Question 3

Which interrupt is unmaskable?

Question 4

Which of the following is hardware generated signal?

Question 5

Consider a system employing an interrupt driven I/O for a articular device that transfers data at an average of 8 KB/s on a continuous basis. Assume that interrupt processing takes about 100 micro seconds (i.e. jump to the interrupt service routine (ISR); execute it and return to the main program). Determine what fraction of processor time is consumed by this I/O device when it is interrupted for every byte.

Question 6

Consider a system in which the bus cycle takes 100 ns. Transfer of bus control from processor to device or device to processor takes 250 ns. One IO device has a data transfer rate of 100 KB/sec and employs DMA. Data are transferred one byte at a time. Suppose we employ DMA in a burst mode. The DMA interface gains bus mastership prior to the start of block transfer and maintains control of the bus until the whole block is transferred. How long would the device tie-up with the bus when transferring a block of 256 bytes ___________(in msec)

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GATE & PSU CS Computer Organization and Architecture

Jan 19GATE & PSU CS