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GATE CS 2022: Computer organization -4
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Question 1
The time for the disk arm to move the heads to the cylinder containing the desired sector is called __________.
Question 2
RISC Instructions support ____Operands Only.
Question 3
Suppose = hit rate of the primary cache
= hit rate of secondary cache
= primary memory hit latency
= secondary memory hit latency
M = time to access information in the main memory
What is the average memory access time experienced by the CPU in this system of two levels of cache?
= hit rate of secondary cache
= primary memory hit latency
= secondary memory hit latency
M = time to access information in the main memory
What is the average memory access time experienced by the CPU in this system of two levels of cache?
Question 4
Which hazard occurs when two instructions need the same hardware resource at the same time?
Question 5
CPU generally handles an interrupt by executing an interrupt service routine_______.
Question 6
Consider we have a 128 KB main memory and 16KB cache size using direct mapping as a mapping technique to cache. Number of tag bits that are required is_______ (given that block size is 256 B).
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