GATE CS 2022: Computer organization -4 (App update required to attempt this test)
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Assume that the control word is 32 bit wide. The micro-instruction format is divided into 3 fields. A micro operation field of 14 bits specifies the micro-operations to be performed. An address selection field specifies a condition based on flags and control memory address field. There are 16 flags. How many bits are in address selection field, address field and the size of control memory in words respectively?
A cache has a hit rate of 95%, 128-byte lines, and a cache hit latency of 5ns. The main memory takes 100ns to return the first word (32 bits) of a line, and 10ns to return each subsequent word. What is the Cache miss penalty of this system? (Assume that the cache waits until the line has been fetched into the cache and then re-executes the memory operation)
Consider the following sequence of micro-operations. MBR←PC MAR←X PC←Y Memory←MBR Which one of the following is a possible operation performed by this sequence?
Question 4Multiple Correct Options
Consider the following processor design characteristics: I. Register-to-register arithmetic operations only. II. Fixed-length instruction format. III. Hardwired control unit. IV. RISC supports less registers.
Which of the characteristics above are used in the design of a RISC processor?
In Pipeline Stage of RISC processor, in which stage, the values are taken from the register?
Consider a 4-stage pipeline where different instruction require different no of cycles at different stages :
How many cycles are required to complete the execution of all 4 instructions?