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GATE CS 2022: Computer organization -2
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Consider a 4- Stage pipeline with respective stage delays of 20ns, 30ns, 40ns & 60ns. Interface register is used between the stages which is having delay of 5ns.What is the performance gain when very large no of instructions are executed?
Which hazard occurs when instruction J tries to write data before instruction, I reads it.
Busy waiting condition occur during which type of interrupt handling mode for I/O
The bit used to signify that the cache location is updated is ________
A computer system supports one address and two address instructions and the word size is 20 bits. Main memory is 128 words. If there are 32 two address instructions than how many one address instructions are used?
Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocks and the request for memory blocks is in the following order: 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 4 , 0 48, Find the number of blocks that will be uncommon in cache when we use FIFO replacement policy and when we use LRU replacement policy __________ ?
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Jul 9GATE & PSU CS
Priya UpadhyayMember since Sep 2020Priya Upadhyay