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GATE CS 2022 : Computer Organization -1 (App update required to attempt this test)

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Question 1

In the absolute addressing mode

Question 2

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while

Question 3

The most appropriate matching for the following pairs
X: Indirect addressing                   1: Loops
Y: Immediate addressing               2: Pointers
Z: Auto decrement addressing       3: Constants

Question 4

The number of 1's in the binary representation of (3 * 4096 + 15 * 256 + 5 * 16 + 3) is

Question 5

Consider a 6-stage pipeline with a cycle time of 3ns, which allows pipelining of all the instruction except memory referenced instructions. Memory referenced instructions suffers from penalty of 4 cycles and 60% of the instruction are M/M referenced instruction. What is the average execution time_________ in nsec.

Question 6

Assume the individual stages of the data path have the following latencies.
Instruction Fetch (IF): 12 ns
Instruction Decode (ID): 8 ns
Execution (EX): 6 ns
Memory (MEM): 9 ns
Write Back (WB): 5 ns
Find the clock cycle time (in ns) in a non-pipelined (single cycle) processor.
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May 21GATE & PSU CS

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Harshita AgarwalHarshita AgarwalMember since Jul 2020
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