GATE CS 2021 : Digital Logic 7 (App update required to attempt this test)
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Initially all the counters are cleared and Y = Output Y = 1 when inputs a2 a1 a0 and b2 b1 b0 are equal. How many clock pulses are needed to get output Y = 1 again __________.
Find the modulus value of the counter.
Choose the correct corresponding excitation table entry for Q(t) =0 and Q(t+1)= 1. Here * denotes don’t care.
If initial state Q1 Q2 Q3 = 1 0 1 after how many cycles it gets to same value
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