Time Left - 15:00 mins

# GATE CS 2021 : Digital Logic 7 (App update required to attempt this test)

Attempt now to get your rank among 574 students!

Question 1

The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0,…) is__________.

Question 2

Consider the following figure Initially all the counters are cleared and Y = Output Y = 1 when inputs a2 a1 a0 and b2 b1 b0 are equal. How many clock pulses are needed to get output Y = 1 again __________.

Question 3

Consider the following synchronous counter made up of JK, D and T flip-flops. Find the modulus value of the counter.

Question 4

A new type of synchronous flip-flop has the following characteristic table. Choose the correct corresponding excitation table entry for Q(t) =0 and Q(t+1)= 1. Here * denotes don’t care.

Question 5

Given a sequential circuit: If initial state Q1 Q2 Q3 = 1 0 1 after how many cycles it gets to same value

Question 6

Which of the following correctly defines Race Around Condition?
• 574 attempts
• 1 upvote
• 1 comment
Sep 15GATE & PSU CS

Posted by: Member since Sep 2020 GradeStack Learning Pvt. Ltd.Windsor IT Park, Tower - A, 2nd Floor, Sector 125, Noida, Uttar Pradesh 201303 [email protected]