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GATE CS 2021 : Digital Logic 6 (App update required to attempt this test)

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Question 1

Let MXI be an inverting 2:1 multiplexer whose output is a’, when s=0 and output is b’ when s =1. That is, MXI(s,a,b) = s’a’ + sb’. What function is the following circuit equivalent to?

Question 2

Consider the following diagram:

DECODER.jpg

Which of the following is represented by the circuit?

Question 3

Aman was implementing 4X16 Decoder using minimum number of 2X4 Decoders with enable Input. The implementation of 4X16 Decoder is given in the following figure.

decod.jpg

Now this Decoder has to be converted to 2X4 Decoder. Aman drew the following diagram.

2x4.jpg

But he was confused what to place in place of W, X, Y, Z out of A, B, C, D. Choose the correct option to help Aman solve the problem correctly.

Question 4

Given a combinational circuit below:

(2 X 1 multiplexer are being used)

What will be the sum min terms at output f?

Question 5

Consider a combinational circuit that converts BCD number to its 9's complement in BCD format only. Let the number of don’t care conditions in this circuit be x and the number of outputs that are negative be y. Then find the value of x - y is _________.

Question 6

A 1-bit full adder takes 20 ns to generate carry-out bit. If the maximum rate of additions is 10 X 106 additions/sec then what is the value of ‘x’ ns for the sum bit when four 1-bit full adders are cascaded?
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Sep 14GATE & PSU CS

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Priya UpadhyayPriya UpadhyayMember since Sep 2020
Priya Upadhyay
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