GATE CS 2021 : Computer organization Rapid Quiz (App update required to attempt this test)
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Consider a computer system which required 256K x 16 bytes of a memory chip. How many rows and columns of 64 Kb memory chips are required to satisfy the above system memory requirement?
Multilevel cache design is used in the computer system to reduce the miss penalty so, consider the following architecture-
10 Memory reference L1-4 misses L2- 2 misses Final level of memory
What will be the GMR, global miss rate and LMR, local miss rate of level 2 cache L2?
Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocks and the request for memory blocks is in the following order: 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 4 , 0 48, Find the number of blocks that will be uncommon in cache when we use FIFO replacement policy and when we use LRU replacement policy __________ ?
A system employs 10 stage instruction pipelines in which 5% instruction results in data dependency, 10% instruction results in control dependency, 2% instructions results in structural dependency. 10% instructions are exposed to data and control dependencies. If the penalty for structural dependency is 1 clock and the penalty for control dependency and data dependency are 3 clocks and 2 clocks respectively. The average instruction time is ________. [in cycles]
The speed gained by an ‘n’ segment pipeline executing ‘m’ tasks is
If following instruction is executed on a system having big endian mechanism implemented.
mov AX, 
where AX is destination register of 16 bits, and memory locations ,  and  contain 20, 24 and 12 respectively. What does the AX register contain at the end of this instruction?