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GATE CS 2021 : Computer organization 7 (App update required to attempt this test)

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Question 1

Suppose after analyzing a new cache design, you discover that the cache has far too many conflict misses and this needs to be resolved. You know that you must increase associativity in order to decrease the number of cache misses. What are the implications of increasing associativity?

Question 2

Multilevel cache design is used in the computer system to reduce the miss penalty so, consider the following architecture-

10 Memory reference L1-4 misses L2- 2 misses Final level of memory

What will be the GMR, global miss rate and LMR, local miss rate of level 2 cache L2?

Question 3

The read access times and the hit ratios for different caches in a memory hierarchy are as given below.

The read access time of main memory is 90 nanoseconds. Assume that the caches use the referred word-first read policy and the write back policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the caches. In execution of a program, 60% of memory reads are for instruction fetch and 40% are for memory operand fetch. The average read access time in nanoseconds (up to 2 decimal places) is______.

Question 4

Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for 500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is _____

Question 5

A 2-level memory system has levels with access time T1 = 15 ns and T2 = 200 ns. The hit ratio for this system is 0.9 . If hit ratio is made to 1 then what will be the new value of T1?

Question 6

A system having 2-level cache L1 and L2 mechanism. The access time of L1 and L2 is 2ns and 6 ns respectively & main memory access time is 100 ns. Hit rate of L1 and L2 is 0.7 & 0.9. Then the average access time is(up to 1 decimal point)
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Oct 26GATE & PSU CS

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Harshita AgarwalHarshita AgarwalMember since Jul 2020
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