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GATE 2023 EDC Quiz 19

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Question 1

The parameter for an ideal n⁺poly-Si gated MOSFET are as follows : L=0.5 μm, w=2.5 μm, t_ox= 10 nm, and V_T= 0.5V

The Gate voltage , V_GS, that must be applied to obtain the I_D-V_D curve shown is ___________(V).

Question 2

Consider an n⁺ polysilicon-silicon dioxide n-type silicon MOS capacitor. Let N_d = 10¹⁵ cm^-3, t_ox =

and

. What will be the flat-band voltage? If

Question 3

In an n-channel MOSFET , drain is shorted to the gate so that V_GS= V_DS. And V_T=1V. If the drain current I_D is 1 mA for V_GS=2V then for V_GS=3V, I_D (in mA) is

Question 4

For a n – channel enhancement MOSFET the parameter are V_TN = .8V, k_n = 5 mA/V², V_GS = 2V. If the transistor is biased in saturation region with I_o = 1 mA . The required

Question 5Multiple Correct Options

Choose the correct answer for the given low-frequency capacitance versus gate voltage characteristics of MOS-capacitor.

Question 6

In a MOS capacitor with an oxide layer thickness of 10 nm the maximum depletion layer thickness is 100 nm. The permittivities of the semiconductor and the oxide layer are ε_s and ε_ox respectively. Assuming ε_s /ε_ox = 3, the ratio of the maximum capacitance to the minimum capacitance of this MOS capacitor is_________

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ESE & GATE EC Electronic Devices and Circuits

May 12ESE & GATE EC