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GATE 2023 Digital Electronics Quiz 71
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Question 1Multiple Correct Options
Binary shift registors are
Question 2
A 4-bit-16 ripple counter uses J-K flip-flop. If the propagation delay of each flip-flop is 50 nanoseconds, the maximum clock frequency that can be used is equal to:
Question 3
A ripple counter is made with three positive edge triggered flip-flops. If the output of previous lower significant bit flip-flop is used as a triggering clock pulse of the next higher significant bit flip-flop, then the resultant counter is a
Question 4
The 5 bit ripple counter which is composed of flip flops with a propagation delay of 20ns, would have the maximum counting speed of
Question 5
A 4-bit right shift register has initialized the value 1000 for (Q3 Q2 Q1 Q0). The D input is derived from Q3, Q2 and Q0 through two XOR gates as shown in figure below. Number of clock pulses required to get pattern 1000 (Q3 Q2 Q1 Q0) again are ________.
Question 6Multiple Correct Options
Consider the following circuit shown in figure below:
The above circuit is 8-bit and left shift register. Suppose D flip flops are initially clear. Then
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Sep 19ESE & GATE EE
