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GATE 2023 Analog Electronics Rank Booster Quiz 40

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Question 1

In the amplifier circuit shown in the fig. FET has IDSS = 2mA and VP = – 1V. The value of R1 required to establish the quiescent drain to ground voltage at 12V is _____ kΩ.

Question 2

Consider a multistage amplifier circuit as shown in the figure below.

The transistor parameter  and= 0.25 mA/V2, and the quiescent drain currents are  = 0.22 mA and  = 0.55 mA respectively. Assuming No-channel length modulation in both the transistor, the value of voltage gain  is equal to-

Question 3

Considering the coupling capacitor are of too higher Values so that on A .C application they become short:

If Vt = 2.0 Volt, = 0.2 mA/V2

Early Voltage Va is 50Volt, Calculate the Rin as seen from the terminal shown in figure while calculating Rin you should consider load resistance RL. Consider the transistor is operating in saturation region.

Question 4

Consider the circuit shown below:

The common drain amplifier is designed as shown in the figure if . The lower cutoff frequency of the circuit is _ Hz.


Question 5

For a p-channel JFET, determine the voltage applied between the gate and source terminal that will result in a drain current of 3 mA, ( Given: IDSS = 9 mA, VP = 8 V )

Question 6

For nMOS and its Transfer curve shown in fig. below, Its region of operation is:

Question 7

Determine the gate threshold voltage in Volt for the enhancement-type MOSFET in the given network, if Given,
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