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GATE 2023 Analog Circuits Quiz 8

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Question 1

In the collector to base bias circuit shown in figure, the value of the RC for

VCC = 15V, VCE = 5V, IC = 5 mA,

hFE = 100 and VBE = 0.7V.

Question 2

For the transistor circuit shown VBE = 0.7 V, β is very high. Then the value of V0 is

Question 3

The value of R for which PMOS transistor in figure will be biased in linear region is

Question 4

In circuit shown FET has IDSS = 15 mA, VP = –5 V calculate, IDS and VDS

Question 5

For the circuit shown below, let β = 75. The Q-point (ICQ, VCEQ) is

Question 6

Find ID and VDS in the FET circuit shown below?

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Aug 24ESE & GATE EC