GATE 2022: Operating System Quiz-7

Consider a program using Run Time Address Binding, generates physical address of 400. The Relocation Register has the value of 200. The corresponding logical/virtual address is

Consider five memory partitions of size 100 KB, 500 KB, 200 KB, 450 KB and 600 KB in same order. If sequence of requests for blocks of size 212 KB, 417 KB, 112 KB and 426 KB in same order come, then which of the following algorithm makes the efficient use of memory?

Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the physical memory. It takes 15 milli sec to search the TLB and 100 millisec to access the physical memory. If the TLB hit ratio is 0.7, the effective memory access time (in millisec) is ________.

A computer uses 30 bit physical address, 38 bit virtual address and uses 2-level paging. The page table base register stores the base address of the first level, each page table, occupied exact one page. Each entry of first level store base address of second level table and each entry of second level table store a page table entry which is of size 32 bits. The size of page in KB in computer is ________.

Consider a paging hardware with a TLB . Assume that the entire page table and all the pages are in the physical memory. If the effective memory access time is 233 msec with TLB hit ratio 0.7 and search time of TLB is 12 msec, the main memory access time is ________ (in msec).

Consider a page size of 1 KB and that each page table entry take 4 bytes. The number of levels of paging required to map a 34-bit virtual address if every page table fits into a single page are ________.