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GATE 2022 : Digital Electronics Quiz 5

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Question 1

10 MHz clock frequency is applied is applied to a cascaded counter of MOD - 2, MOD - 5, MOD - 4 counter. what is the lowest output frequency (KHz)?

Question 2

For the circuit given, if the clock frequency is ‘f’ Hz, then the frequency of the output Q is:


Question 3

Each state is designated as Q1Q0 let initial state to be 00 then state transition sequence is _________.


Question 4

An x-y flip-flop, whose characteristic table is given below is to be implemented using J-K flip flop.

Question 5

In a 4 bit modulo -6 ripple counter the proportional delay of J-K Flip flop is 50 ns. What is the max clock frequency that can used without skipping a count?

Question 6

Consider a sequential circuit using three J – K flip flops and one AND gate shown in figure, output of the circuit becomes ‘1’ after every N clock cycles. The value of N is-

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Aug 17ESE & GATE EE