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GATE 2020 National Champion Quiz : (Computer Organizations)

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Question 1

If pipeline depth for a particular processor is K, which of the following is true?

Question 2

Effective address is calculated by adding or subtracting displacement value to

Question 3

CPU performance is dependent upon Instruction Count, CPI (Cycles per instruction) and Clock cycle time. All these three are affected by

Question 4

Consider the following sequence of micro-operations:
MBRPC
PCY+PC
MemMBR
The addressing mode and operation depicted are respectively

Question 5

Consider a 4-stages pipeline with respective stage delays of (10ns, 5ns, 20ns & 15ns) .What is the efficiency of the pipeline when the number of tasks are significantly larger than the number of stages?

Question 6

Techniques that automatically move program and data blocks into the physical Main Memorywhen they are required for execution are called

Question 7

Consider the expression Let X be the minimum number of registers required by an optimal code generation (without any register spill) algorithm for a load/store architecture in which (i) only loads and store instructions can have memory operands and (ii) arithmetic instructions can have only register or immediate operands. The value of X is _____.

Question 8

A hard disk with a transfer rate of 10 Mbytes/second is constantly transferring data to memory using DMA. The processor runs at 600 MHz, and takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 20 Kbytes, what is the percentage of processor time consumed for the transfer operation?

Question 9

Consider two processors P1 and P2 executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P2 takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on P1. If the clock frequency of P1 is 1GHz, then the clock frequency of P2 (in GHz) is _________.

Question 10

A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as a direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits.

Question 11

Consider a machine with a byte addressable main memory of bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is ______.

Question 12

Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC- relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence.

If the target of the branch instruction is i, then the decimal value of the Offset is _____.
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Jan 17GATE & PSU CS

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Richa TiwariRicha TiwariMember since Feb 2019
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