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GATE 2020 : Computer Organization & Architecture Quiz 7 (App update required to attempt this test)

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Question 1

Assume the following cache memory design: 16 bit addresses, byte addressable, cache size is 256 bytes, block size is 8 bytes, tag size is 11 bits. Find the associativity of cache.

Question 2

Consider 4-block cache (initially empty) with the following main memory block references.
4, 5, 7, 12, 4, 5, 13, 4, 5, 7
Identify the hit ratio for Direct mapped cache?

Question 3

Consider the cache memory of size 16KB with Block Size 64B. Consider two approaches for memory design: Direct mapped cache, Fully Associative cache. For the hexadecimal main memory addresses 111111, 666666, what will be the tag values for direct mapped cache and fully associative cache respectively?

Question 4

Consider a cache consisting of 128 blocks of 16 words each. Main memory has 64 K words and given main memory is 16 bit addressable. Assuming tag memory cost is defined as 1 Rs/bit. X and Y are respective costs of tag memories ( in Rs) for Direct mapping and Associative mapping. Find the value (in Rs) of 3X+2Y.

Question 5

Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocks and the request for memory blocks is in the following order:
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155
Which one of the following memory block will NOT be in cache if LRU replacement policy is used?

Question 6

A two way set associative cache has lines of 16 byte and a total cache size of 8 K bytes. The 256 M byte main memory is byte addressable. Which one of the following main memory block is mapped on to the set ‘0’ of the cache memory?

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GATE & PSU CS Computer Organization and Architecture

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