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GATE 2020 : Computer Organization & Architecture Quiz 6 (App update required to attempt this test)

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Question 1

Consider a two-level cache hierarchy with L1 and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache 0.1, the L2 cache experiences, on average, 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is _____.

Question 2

A cache has a hit rate of 95%, 128-byte lines, and a cache hit latency of 5ns. The main memory takes 100ns to return the first word (32 bits) of a line, and 10ns to return each subsequent word.
What is the Cache miss penalty of this system? (Assume that the cache waits until the line has been fetched into the cache and then re-executes the memory operation)

Question 3

A computer has 164 memory subsystem with the higher order inter-leaving using 82 chips for computer system with an 8-bit address bus. The number of RAM chips needed are____.

Question 4

Given Ts : Transfer time
B : Number of bytes to be transferred
N : Number of bytes on a track
R : Rotational speed.
Which of the following expression gives the total aveage access time?

Question 5

In a C program, an array is declared as float a [2048]. Each array element is 4Bytes in size, and the starting address of the array is 0×00000000. This program is run on a computer that has a direct mapped data cache of size 8 Kbytes, with block (line) size of 16 Bytes.
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Which elements of the array conflict with element a [0] in the data cache? Justify your answer briefly.

Question 6

Let access time of cache is s. Time required for block access is and the hit ratio is 0.7. The average time for the CPU to access a word in two level memory is given by
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Richa TiwariRicha TiwariMember since Feb 2019
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