Digital Electronics GATE Questions
The Digital Electronics GATE questions PDF is shared on the page below. This Digital Electronics GATE questions PDF contains some of the best questions asked from the subject in the GATE examination in recent years.
Download Digital Electronics GATE Questions PDF
Information About Digital Electronics GATE Questions
The GATE Electronics and Electrical exam will check one's understanding of the subject in various ways, including theoretical questions, MCQs, MSQs, etc. Other information about Digital Electronics GATE questions is shared in the points below.
- Digital Electronics carries a weightage of 12-13 marks in the GATE EE exam, making it an important subject for aspirants to prepare for.
- The questions in the Digital Electronics section of GATE are designed to test understanding of the fundamental concepts of digital circuits, logic gates, and binary numbers.
- The questions can range from basic to complex, and it is essential to have a thorough understanding of the subject to score well in this section.
Digital Electronics GATE Questions with Answers
The Digital Electronics GATE questions with answers are shared for the candidates below. Through these questions and answers, candidates get a view of the types and topics from which questions are asked. The questions are shared below.
Question 1: The number of comparators required in a 3-bit comparator type ADC is
(GATE ECE 2002)
Question 2: The number of comparators in 4-bit flash ADC is
(GATE ECE 2000)
Question 3: A traffic signal cycles from GREEN to YELLOW, YELLOW to RED and RED to GREEN. In each process, GREEN is turned on for 70 seconds, YELLOW is turned on for 5 seconds, and the RED is turned on for 75 seconds. This traffic light has to be implemented using a finite state machine (FSM). The only input to this FSM is a clock
of 5 second period. The minimum number of flip-flops required to implement this FSM is _______
(GATE ECE 2018)
Question 4: In a DRAM,
(GATE ECE 2017 Set 2)
a. Periodic refreshing is not required
b. Information is stored in a capacitor
c. Information is stored in a latch
d. Both read and write operations can be performed simultaneously
Question 5: A 16 Kb (=16,384 bit) memory array is designed as a square with an aspect ratio of one (the number of rows equals the number of columns). The minimum number of address lines needed for the row decoder is
(GATE ECE 2015 Set 1)
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