Data Hazard
By BYJU'S Exam Prep
Updated on: September 25th, 2023
Data hazard, structural hazard, and control hazard are three categories of common hazards. Hazards in the domain of central processing unit (CPU) design are problems with the instruction pipeline in CPU micro-architectures when the next instruction cannot execute in the next clock cycle, which might possibly result in inaccurate calculation results.
Data hazard arises if an instruction accesses a register that a preceding instruction overwrites in a future cycle. Unless we decrease data hazard, pipelines will produce erroneous outputs. In this article, we shall dig further into Data Hazards.
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Table of content
What is a Data hazard?
Data hazard in pipelining arises when one instruction is dependent on the results of a preceding instruction and that result has not yet been calculated. Whenever two distinct instructions make use of the same storage. The location must seem to be run sequentially.
In other words, a Data hazard in computer architecture occurs when instructions with data dependency change data at several stages of a pipeline. Ignoring possible data hazards might lead to race conditions (also termed race hazards).
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Types of Data Hazard in Pipelining
The data hazard or dependency exists in the instructions in the three types that are as follows:
- Read after Write (RAW)
- Write after Read (WAR)
- Write after Write (WAW)
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Read after Write (RAW)
Read after Write(RAW) is also known as True dependency or Flow dependency. A read-after-write (RAW) data hazard is when an instruction refers to a result that has not yet been computed or retrieved. This can happen because, even when an instruction is executed after another, the previous instruction has only been processed partially through the pipeline.
For example, consider the two instructions:
I1. R2 <- R5 + R3
I2. R4 <- R2 + R3
The first instruction computes a value to be saved in register R2, and the second uses this value to compute a result for register R4. However, in a pipeline, when the operands for the second operation are retrieved, the results of the first operation have not yet been stored, resulting in a data dependence.
Instruction I2 has a data dependence since it is dependent on the execution of instruction I1.
Write after Read (WAR)
Write after Read(WAR) is also known as anti-dependency. These data hazards arise when an instruction’s output register is utilized immediately after being read by a previous instruction.
As an example, consider the two instructions:
I1. R4 <- R1 + R5
I2. R5 <- R1 + R2
When there is a chance that I2 will end before I1 (i.e., when there is concurrent execution), it must be assured that the result of register R5 is not saved before I1 has had a chance to obtain the operands.
Write after Write (WAW)
Write after Write(WAW) is also known as output dependency. These data hazards arise when the output register of instruction is utilized for write after the previous instruction has been written.
As an example, consider the two instructions:
I1. R2 <- R4 + R7
I2. R2 <- R1 + R3
The write-back (WB) of I2 must be postponed until I1 has completed its execution.
Handling Data Hazard
There are various methods to handle the data hazard in computer architecture that occur in the program. Some of the methods to handle the data hazard are as follows:
- Forwarding is the addition of specific circuitry to the pipeline. This approach works because the needed values take less time to travel via a wire than it does for a pipeline segment to compute its result.
- Code reordering requires the use of specialized software. This sort of software is known as a hardware-dependent compiler.
- Stall Insertioninserts one or more installs(no-op instructions) into the pipeline, delaying execution of the current instruction until the needed operand is written to the register file; unfortunately, this method reduces pipeline efficiency and throughput.
